A conventional TTL output circuit or buffer commonly used in TTL output devices is illustrated in FIG. 1. The output buffer circuit 10 delivers binary logic output signals V.sub.0 of high or low potential at the signal output 12 in response to binary logic signals V.sub.1 of low or high potential at the signal input 14. The Darlington transistor pair Q4 and Q4A constitute the pull-up transistor element for sourcing current to the signal output 12 from high potential source V.sub.CC for establishing a high potential or logic high level signal V.sub.OH at the output 12. Pull-down transistor element Q3 sinks current from the signal output 12 to low potential or ground for establishing a low potential or logic low level output signal V.sub.OL at the output 12. Resistor R3 and diode SD3 provide an effective squaring network for giving the circuit a square transfer curve. The respective conducting states of the pull-up and pull-down transistor elements are controlled by the phase splitter transistor element Q2.
The feedback diode SD1 provides a large current sinking capability for transition at the output from high to low potential. Feedback diode SD2 drains the base of pull-up transistor Q4. The feedback current from the output through Schottky diode SD1 is received by phase splitter transistor Q2 and applied to the base of pull-down transistor Q3. As further explained, the increased output sinking current through pull-down transistor Q3 by reason of the feedback diode SD1 is proportional to .beta..sup.2 during the transition from high to low logic level at the signal output 12, where .beta. is the transistor gain.
The TTL output circuit 10 is inherently inverting. When a low potential or low logic level input signal V.sub.I appears at the signal input 14, the base drive current I.sub.1 to phase splitter transistor Q2 through base drive resistor R1 and input transistor Q1 is diverted by input transistor Q1 and the phase splitter transistor Q2 is non-conducting. Pull-down transistor Q3 is therefore also non-conducting. Base drive current from power supply V.sub.CC passes through resistor R2 to the respective bases of the pull-up transistor element, Darlington transistor pair Q4A and Q4, delivering a logic high level or high potential at the signal output 12.
A high level or high potential signal at the signal input 14 results in a transition from high to low potential at the signal output 12. Base drive current I.sub.1 is delivered through input transistor Q1 turning on the phase splitter transistor Q2 which in turn delivers base drive current I.sub.4 to the pull-down transistor element Q3. With phase splitter transistor Q2 and pull-down transistor Q3 conducting, the base drive current is diverted from the pull-up transistor element Darlington pair and the pull-up transistor element is non-conducting. Pull-down transistor element Q3 sinks current from the signal output 12 and a low level or low potential signal V.sub.OL appears at the signal output 12.
A graph of the output current vs. voltage (I-V) characteristic in the low state at the signal output 12 is illustrated in FIG. 1A. There are five distinct regions in this graph. The first region, which is not of particular interest to this discussion. Is at I.sub.OL =0 along the horizontal axis before the first bend in the I-V curve. This is the offset region of the pull-down transistor element Q3. After the first bend in the curve is Region II of the characteristic curve which is the saturation region of pull-down transistor element Q3. The output characteristic has a low impedance in this region since the output voltage V.sub.OL changes very little in this region as the output current I.sub.OL is increased. The corresponding output voltage is: EQU V.sub.01 .congruent.V.sub.SAT Q3. (1)
As the output current is further increased, the output characteristic enters a high impedance region where the output current increases very little as the output voltage is increased. This is Region III and corresponds to the linear region of the pull-down transistor element Q3. The corresponding output current in this case is: EQU I.sub.01 =.beta.I.sub.4, (2)
where .beta. is the current gain of the pull-down transistor element Q3.
As the output voltage increases, a voltage is reached that will forward bias the feedback Schottky diode SD1. This allows current to pass through the Schottky diode into the collector of phase splitter transistor Q2 and subsequently through the emitter of Q2 into the base of Q3. This is Region IV of the output low state I-V characteristic curve. It is a low impedance region in which the output voltage is given by the expression: EQU V.sub.02 =V.sub.BE Q3+V.sub.SAT Q2+V.sub.SD1. (3)
As the output current is increased, phase splitter transistor Q2 will come out of saturation and enter the linear region. This is Region V of the output curve which is characterized by high impedance, i.e., the output current changes very little with increasing output voltage. In this region the output current is equal to the current through the collector of pull-down transistor Q3 plus the current through SD1, or: EQU I.sub.02 =I.sub.C Q3+I.sub.5.
When phase splitter transistor Q2 enters the linear range, the maximum value of I.sub.5 becomes limited by .beta. times the base current to Q2 which is the current I.sub.1, i.e.: EQU I.sub.5 =.beta.I.sub.1.
Since Q3 is in its linear region, the Q3 collector current is .beta. times the Q3 base current, hence: EQU I.sub.C Q3=.beta.I.sub.4.
But, EQU I.sub.4 =I.sub.E Q2-I.sub.3. EQU I.sub.4 =(.beta.+1)I.sub.1 -I.sub.3. (4)
Therefore, EQU I.sub.02 =.beta.((.beta.+1)I.sub.1 -I.sub.3)+.beta..sup..beta.. EQU I.sub.02 =.beta..sup.2 I.sub.1 +2 .beta..sup.I.sub.1 =.beta..sup.I.sub.3.
Since EQU 2.beta.I.sub.1 -.beta.I.sub.3 &lt;&lt;.beta.2.sup.I.sub.1, for reasonable values of .beta., EQU I.sub.02 .congruent..beta..sup.2 I.sub.1. (5)
Consequently, the highest current limited region of the device is limited by the square of the current gain of the transistors.
From this the characteristic output of the circuit of FIG. 1 has five operating regions, three of which are characterized by high impedances (Regions I, III, and V) and two of which are characterized by low impedances (Regions II and IV). Since the output structure shown in FIG. 1A is usually tied to a transmission line, the best performance is achieved by making the effective impedance of the output as low as possible. This is accomplished by establishing the low impedance regions at the lowest possible voltages. Since Region I is already as narrow as possible given other constraints on the characteristics of transistor Q3, the objective is to make Region III as narrow as possible, and to make Regions II and IV as wide as possible.
A problem with the conventional TTL output circuit 10 of FIG. 1 is that the power level P of the device is determined by I.sub.1 and I.sub.2. EQU P=V.sub.CC (I.sub.1 +I.sub.2). (6)
A large initial sinking current I.sub.01 at the level for example shown in FIG. 1A requires a relatively small collector resistor R2 and relatively large collector current I.sub.2 which increases the power consumption of the buffer. To reduce power dissipation, the collector resistor R2 is selected to be large and collector current I.sub.2 small. As a result the initial sinking current I.sub.01 is also small. To achieve the desired .beta..sup.2 or high current sinking mode I.sub.02 a higher corresponding output voltage V.sub.02 for the logic low level or low potential signal V.sub.OL is required. At this level the low level output voltage V.sub.02 is in the vicinity of the transition voltage 2V.sub.BE of typical TTL buffers. EQU V.sub.02 .congruent.2V.sub.BE. (7)
A disadvantage of the prior art TTL output buffer transition characteristic is that the low level output voltage V.sub.02 corresponding to output sinking current I.sub.02 in the high current sinking mode may not be unambiguously separated from the transition voltage threshold for TTL devices which is approximately 2V.sub.BE. As a result receivers or internal buffers on the transmission line or common bus coupled to the signal output 12 of output circuit 10 may not recognize the low level voltage signal V.sub.OL when a transmission line step occurs at level V.sub.02 and will therefore experience transmission line delay. Furthermore the receivers or internal buffers may oscillate when V.sub.02 is in the vicinity of 2V.sub.BE. It is desirable that V.sub.02 look like a logic low or zero for switching the receivers on the transmission line or common bus. To assure unambiguous separation of the higher drive low level voltage signal V.sub.02 at the signal output 12 below the switching threshold of 2V.sub.BE the typical TTL output buffer 10 may require high power dissipation to increase the current I.sub.01 at which pull-down transistor Q3 comes out of saturation. This will ensure that the transmission line step occurs at V.sub.01 rather than V.sub.02.
The TTL output buffer 10 of FIG. 1 is applicable for TTL bistate devices. For TTL tristate output devices capable of establishing a high impedance third state at the signal output 12, modification of the TTL output buffer is required as illustrated in FIG. 2. In the TTL tristate output buffer 20 illustrated in FIG. 2, elements corresponding in function to the TTL bistate output buffer 10 of FIG. 1 are indicated by the same reference designations. An enable signal input 16 is added for establishing the high impedance third state. In order to retain the feedback diodes SD1 and SD2 while also including the enable input 16, dual phase splitter transistors Q2 and Q2' are required, generally connected in current mirror configuration. In this configuration the emitters of dual phase splitter transistors Q2 and Q2' are coupled in parallel to the base of pull-down transistor Q3 for jointly controlling the conducting state of the pull-down transistor element. The bases of phase splitter transistors Q2 and Q2' are also tied together at the collector of input transistor Q1. The collector of the second phase splitter transistor Q2' is coupled through its own collector resistor R2' and diode SD2' to the power supply V.sub.CC.
The enable input 16 is connected through diode SD4 to the base of the pull-up transistor element, Darlington transistor pair Q4A and Q4, for disabling the pull-up transistor element when a low level or a low potential enable signal E appears at the enable input 16. Enable input 16 is also tied through diode SD5 to the bases of the dual phase splitter transistors Q2 and Q2' so that they are also disabled by a low level enable input signal E. With phase splitter transistors non-conducting, the pull-down transistor Q3 is also disabled. As a result the tristate output device 20 constitutes a high impedance at the signal output 12 coupled to a transmission line or common bus and appears to receivers or internal buffers on the transmission line as if it were not there. The output device 20 operates in the normal bistate mode when a high level enable signal appears at the enable input 16.
The dual phase splitter transistors Q2 and Q2' are required so that only the collector of phase splitter transistor Q2 is connected to the base of the pull-up transistor element for controlling the conducting state of the pull-up transistor element. The enable input 16 is connected only to the collector of phase splitter transistor Q2. The collector of phase splitter transistor Q2' is not connected to the enable input 16. Rather, the feedback diodes SD1 and SD2 from the signal output 12 are coupled only to the collector of phase splitter transistor Q2'. There is no direct coupling therefore between the signal output 12 and the enable input 16 which would otherwise destroy the high impedance third state. Thus, the dual phase splitters Q2 and Q2' are required in the conventional tristate output buffer 20 in order to include both the enable input coupling 16 and the feedback diodes SD1 and SD2. The blocking diode SD2' blocks any current flow from the signal output 12 through the device to the power supply V.sub.CC.
A disadvantage of the conventional tristate output buffer 20 in addition to the requirement that dual phase splitter transistors and accompanying circuit elements be included in the output buffer is that the full square law enhancement or .beta..sup.2 step-up of the output current affording a high current sinking mode during transition from high to low level voltage at the signal output 12 may be lost. The loss of .beta..sup.2 high current sinking mode may result because of "current hogging" of base drive current by phase splitter transistor Q2 while transistor Q2 is saturated. The dual phase splitter transistor Q2' which receives the feedback current through the feedback diodes SD1 and SD2 from the signal output 12 therefore has virtually no base drive when it enters the linear operating region. As a consequence, the collector current of Q2 is not determined by its current gain .beta., but rather by emitter current of Q2 in saturation when it is "hogging" the base drive to the pair of transistors Q2 and Q2'.